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STV1601A
SERIAL INTERFACE TRANSMISSION ENCODER
THIS IC CONTAINS ALL THE CIRCUITS NEEDED FOR CONVERSION FROM PARALLEL DATA, AND PARALLEL CLOCK, INTO SERIAL DATA. APPLICATIONS ARE STRAIGHTFORWARD AS ONLY A FEW EXTERNAL COMPONENTS ARE NEEDED. OTHER RELATED IC's INCLUDE : STV1602A, A SERIAL TRANSMISSION DECODER (WITH A BUILT-IN CABLE EQUALIZER AND PARALLEL-TO-SERIAL CONVERSION) STV1389AQ COAXIAL CABLE DRIVER STRUCTURE Hybrid IC CODE LIMITATION The word composing the Sync word listed above shall not appear during data words. This limitation includes 00 and FF in 8-bit use and 000 through 003 and 3FC through 3FF in 10-bit use. DESCRIPTION The STV1601Ais a Hybrid IC encoder that converts parallel data into serial data for a serial transmission line.
. . . . . . . . . . . . .
APPLICATIONS SERIAL DATA TRANSMISSION ENCODER 100 to 270 Mb/s APPLICATIONS EXAMPLES Serial data transmission of digital television signal 525-625 lines 4:2:2 component 270Mb/s (10-BIT) 4*FSC PAL composite 177Mb/s (10-BIT) 4*FSC NTSC composite 143Mb/s (10-BIT) FUNCTIONS Parallel-to-serial conversion Scrambler : Modulo - 2 division by G(x) = (x9 + x4 + 1) (x + 1) PLL for serial clock generation PLL lock detection Sync word required with the parallel data stream
8 bit 1st word 2nd word 3rd word FFH 00H 00H 10 bit 3FFH 000H 000H
LST RSE V CC PCX PCY GND FV TRP TN1 PCK 28 29 30 31 32 33 34 35 36 37 NC 1 2
PGA37 (Ceramic Package) ORDER CODE : STV1601A
PIN CONNECTIONS
D0Y D0X D1Y D1X D2Y D2X D3Y 19 18 17 16 15 14 13 12 11 10 3 SX 4 SY 5 GND 6 D9X 7 D9Y 8 D8X 9
1601A-01.EPS
V EE 27
V EE 26
25
24
23
22
21 20
D3X D4Y D4X D5Y D5X D6Y D6X D7Y D7X
GND
Sync word conversion (8-bit timing reference signal is internally converted to 10-bit).
November 1992
D8Y
1/17
STV1601A
PIN DESCRIPTION
Pin Symbol N Equivalent circuit Description I/O Standard Min. Typ. Max. Unit
GND 4k
V CC
1
LST
1
PLL lock detection. Is High while PLL locked. If unlocked, becomes irregular. At free running (TN1 H) turns Low H L
O
-1.0 -4.0
V V
2k VEE
2k
1601A-02.EPS
GND 600 600
36
PCK
36
Clock output frequency divided to 1/10 VCO output. Used to check VCO free running frequency H L
O
-0.8 -1.6
V V
240 V EE
GND
VCC
3
SX
30 4
10 0
100
VCC
1601A-03.EPS
30 3
VR3
1601A-04.EPS
2k VEE
115
2k
2/17
1601A-01.TBL
4
SY
Differential Serial Output Input parallel data is converted to serial, then from scrambled NRZ to NRZI data H L
O
-1.6 -2.4
V V
STV1601A
PIN DESCRIPTION (continued)
Pin Symbol N Equivalent circuit Description Parallel data and clock input buffers power supply. When this pin is connected to +5V, parallel data clock turns to TTL mode. When this pin is connected to GND, parallel data clock turns to ECL mode. I/O Standard Min. Typ. Max. Unit
29
VCC
29 1k
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
D9X D9Y D8X D8Y D7X D7Y D6X D6Y D5X D5Y D4X D4Y D3X D3Y D2X D2Y D1X D1Y D0X D0Y
6
7 V R3
2k V EE
GND
2k
1601A-05.EPS
Parallel input ports: LSB : D0X or Y MSB : D9X or Y Signal : DnX Return : DnY For ECL mode, VCC shalll be 0V H L ForTTL mode, VCC shall be +5V H L
-1.0 -1.6 2.0 0.8
V V V V
28
28
RSE
70k
VCO range selection H : high range 140 to 270MHz L : low range 100 to 145MHz H L
I -0.4 -4.0 V V
10k
10k
1601A-06.EPS
V EE
3/17
1601A-02.TBL
STV1601A
PIN DESCRIPTION (continued)
Pin Symbol N
VCC 2k 2k
Equivalent circuit
Description
I/O
Standard Min. Typ. Max. Unit
30
PCX Parallel clock (PCX) and its return (PCY) For ECL mode, VCC = 0 H L For TTL mode, VCC = +5V H L I -1.0 -1.6 2.0 0.8 V V V V
30
31 V R3
31
PCY
1601A-07.EPS
2k VEE
2, 5, 32 26 27
GND VEE VEE
GND
GND -5V power supply I/O buffer PLL -5V power supply Logic part
VCC
-5.2 -5.2 I
-5.0 -5.0
-4.8 -4.8
V V
0.022F
33
FV
1k 1k 1k 2F 0.1F
1601A-08.EPS
220
34 33
VCO free running frequency adjustment : VEE level gives the lowest frequency. To adjust, set TN1 high.
-3.9
V
34
TRP
VE E
1k
1k 10k
V9
VCO input and phase comparator output should be connected to a parallel clock frequency trap filter to minimize jitter
O -3.2 V
VCC
GND 12k
20k
35
TN1
1 VR3 4k
1601A-09.EPS
Test mode : High : VCO free running condition (input disabled) Low : Normal mode (input enabled)
I -1.0 -4.5 V V
VEE
4/17
1601A-03.TBL
STV1601A
BLOCK DIAGRAM
PCY PCX 31 30 TN1 35 FV 33 TRP 34 RSE 28 PCK 36
37 N.C.
LST
1
PLL LOCK DE TECTOR
PHAS E DETECT OR
VCO
TIMING GENERATOR
2
GND
Parallel Clock
5 SX 3
NRZ NRZI X + X + 1 SCR AMBLER
9 4
GND
Parallel Load
Serial Clock
SY
4
PAR ALELL TO SERIAL CONVER TER
32 GND
26 V EE
10-BIT X 3 WORD SHIFT REGISTER
000hex DETECTO R
27 V EE
29 V CC
6 D9X
7 D9Y
8 D8X
9 D8Y
10 11 D7X D7Y
12 D6X
13 D6Y
14 15 D5X D5Y
16 D4X
17 18 D4Y D3X
19 D3Y
20 21 D2X D2Y
22 D1X
23 24 D1Y D0X
25 D0Y
ABSOLUTE MAXIMUM RATINGS
Symbol VEE VCC VIN IOUT Toper Tstg PD Parameter Supply Voltage Supply Voltage Input Voltage Output Current Operating Temperature Storage Temperature Allowable Power Dissipation Value -6 +6 VEE to VCC -30 0 to 65 -50 to 125 2.0 Unit V V V mA o C o C W
RECOMMENDED OPERATING CONDITIONS
1601A-05.TBL 1601A-06.TBL
Symbol VEE VCC Toper
Parameter Supply Voltage Supply Voltage * Operating Temperature
Value -4.8 to -5.2 4.8 to 5.2 0 to 65
Unit V V o C
* For TTL input. Voltages are given with respect to GND
ELECTRICAL CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA = 25oC unless otherwise speciied)
Symbol IEE ICC Parameter Supply Current 1 Supply Current 2 Test Conditions Test Circuit Min. Typ. 140 7 Max. Unit mA mA 5/17 DC CHARACTERISTICS Figure 2
1601A-04.TBL
1601A-10.EPS
STV1601A
ELECTRICAL CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA = 25oC unless otherwise speciied)
Symbol VIH VIL VIH VIL IIH IIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL fMAX1 fMIN1 fMAX2 fMIN2 fHP1 fLP1 fHP2 fLP2 fHP3 fLP3 fOP1 fOP2 tjit Parameter Test Conditions VCC = GND PCX, PCY, DnX, DnY VCC = +5V PCX, PCY, DnX, DnY Input Current PCX, PCY, DnX, DnY RSE Input Voltage TN1 PCK R P = 1k Output Voltage LST IOH = -10A, IOL = +10A SX, SY R P = 220 VCO VCO VCO VCO Max. Oscillation Frequency 1 Min. Oscillation Frequency 1 Max. Oscillation Frequency 2 Min. Oscillation Frequency 2 Figure 4 30.0 14.0 15.0 10.0 Figure 1 27.7 25.5 18.8 16.5 15.0 14.0 10.0 Figure 8 13.0 27.0 14.5 Figure 5 -1.0 -4.0 -1.6 -2.4 Figure 6 Figure 3 Figure 7 Test Circuit Min. -1.0 -1.6 2.0 0.8 5 +1 -4.0 -1 -4.5 -0.8 -1.6 Typ. Max. Unit V V V V A A V V V V V V V V V V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz DC CHARACTERISTICS
Input Voltage
-1 -0.4
AC CHARACTERISTICS RSE = "H" RSE = "L" f signal = 270MHz RSE = "H" PLL Pull in Range f signal = 177MHz RSE = "H" f signal = 143MHz RSE = "H" PLL Generator Frequency Jitter RSE = "H" RSE = "L" f signal = 270MHz RSE = "H"
0.25 nsec
Tested through PCK : 1/10 of serial clock.
SWITCHING CHARACTERISTICS (VEE = -5V, VCC = GND/+5V, TA = 25oC unless otherwise speciied)
Symbol tr tf tr tf Parameter Rise Time Fall Time Rise Time Fall Time Test Conditions PCK R P = 1k SX, SY R P = 220 Test Circuit Min. Typ. 0.8 1.4 0.7 0.7 Max. Unit nsec nsec nsec nsec
Figure 10
TIMING RELATION OF INPUT CLOCK AND DATA
Pulse Width Delay Time
1601A-09.TBL
Symbol tw td
Parameter
Test Conditions PCX, PCY PCX - Dn
Test Circuit Figure11
Min. -5 + tc/2 -5
Typ. tc/2
Max. Unit +5 + tc/2 nsec +5 nsec
6/17
1601A-08.TBL
1601A-07.TBL
INPUT LEVEL
TTL ECL VEE -5V 10/16V -5V 10/16V
0.1
+1.4V -1.3V
+5V GND
VR
VCC
10/16V
0.1
0.1
0.1
0.1
2
5
32
29
27
26
GND
VCC INPUT SELECT N.C. 37 FREQUENCY MONITOR
VEE
30 PCX
2
GND 3 A SW2
32 ADS
24 27 30 23
8
V EE SYN 20 EVR 21 PCK 19 D0 18
7
31 PCY
-5V
1k PCK 36 -5V
PLL LOCK DETECTOR 10k
A B
CABLE INPUT DIGITAL INPUT SY SX 4
Figure 1 : Test Circuit Diagram Example
6
D9X
TRS DETECTOR SIGNAL FREQENCY MONITOR 1k x 4
7
D9Y
8
D8X
9
D8Y
10 D7X
LST
1 220
0.1 75
B 10F 29 CX
D1 17
-5V
11 D7Y 0.1 SX
STV1389AQ
1 220
31 MON 100
0.1
75
SERIAL OUT
0.1
1k x 8 D2 16
D3 15
HP8182A SIGNAL ANALYZER
12 D6X
3
13 D6Y
0.1
14 D5X
15 D5Y 220
220 220
D.U.T. STV1601A
SY
4 2
220
28 QFS 41pF 26 AIX
16 D4X 150 -5V 0.1 73 0.1
41pF
150
SERIAL IN
STV1602A
D4 14
D5 13 D6 12 D7 11 D8 10 25 AIY
D9 9
17 D4Y -5V 0.1
150pF TRP 34 0.22H
18 D3X
-5V
HP8180A
19 D3Y
20 D2X
SIGNAL GENERATOR
21 D2Y
-5V
33 DIX
22 D1X 10F/10V TN1 35
22k -5V
22k TN1
0.1 6 220
10F 34 DIY
220 220
23 D1Y SW2 ON : AF FREQUENCY ADJUST
24 D0X
25 D0Y
QSW
RSE ESO ESI 22 1 37
FV
5
DPR 36 35
SW3 ON : AF FREQUENCY ADJUST
FV
RSE
33
28
-5V
0.1 100k
330
LED
SW1 A
VCO RANGE SELECT A B LOW RANGE HIGH RANGE 10k 0.1
B
10k
V R1
VCO FREQUENCY ADJUST
-5V
-5V
VCO FREQUENCY V R2 ADJUST
-5V
-5V
STV1601A
7/17
1601A-11.EPS
STV1601A
Figure 2
V CC +5V I CC A 10/16V 0.1 A 10/16V V EE -5V I EE
0.1
2
5 GND
32
29 V CC
27
26
V EE 1k PCX 30
STV1601A
220 SX 3 220 SY 4 -5V 0.1F
FV 33
RSE 28
TN1 35
10F SW1 22k
SW1
POSITION ON
V R1 -5V -5V
Figure 4
-5V V1 -0.8V -1.6V V2 -1.6V -0.8V A1 I IH I IL A2 I IL I IH 10/16V
0.1
2
5 GND
32
29 V CC
27
26
V EE 1k PCX 30
30 PCX
31 PCY
STV1601A
220 SX 3 220
11
12 FV 33 RSE 28
SY TN1 35
4
-5V 0.1F
V1
V2 10F SW1 B 10k V R1 -5V -5V -5V A
1601A-13.EPS
SW2 22k
SW1 SW2
POSITION ANY ON
8/17
1601A-12.EPS
10k
STV1601A
Figure 4
-5V 10/16V
0.1
2
5 GND
32 29 V CC
27 26 V EE PCX 30
FREQUENCY MONITOR 1k
STV1601A
220 SX 3 220 SY 4 -5V 0.1F
FV 33
RSE 28
TN1 35
10F SW1 B 10k V R1 -5V -5V -5V A 22k SW2
POSITION SW1 A B SW2 ON ON VCO RANGE HIGH LOW
1601A-14.EPS
Figure 5
-5V V1 -0.8V -1.6V V2 -1.6V -0.8V V VOH VOL 0.1 10/16V
2
5 GND
32 29 V CC
27 26 V EE
30 PCX
31 PCY
STV1601A
LST
1 V
V1
V2
FV 33
RSE 28
TN1 35 POSITION ANY OFF
10F SW1 B 10k V R1 -5V -5V -5V A SW2 22k
SW1 SW2
9/17
1601A-15.EPS
STV1601A
Figure 6
-5V 10/16V
Figure 7
-5V 10/16V
0.1
0.1
2
5
32 29 V CC
27 26 VEE
2
5 GND
32 29 V CC
27 26 V EE PCX 30
GND 31 TN1 V1
FREQUENCY MONITOR 1k
30 PCX
STV1601A
28 RSE LST 1 V V1
STV1601A
220 SX 3 220 SY 4 -5V 0.1F
31 PCY FV 33 -0.8V -1.6V RSE 28
FV 33
TN1 35
10F SW2
1601A-16.EPS
10k V R1 -5V
22k
VR1 -5V -5V
Figure 8
-5V 10/16V
0.1
TRIGGER
2
5 GND
32
29 V CC
27 26 VEE PCX 30
FREQUENCY MONITOR 1k -5V
STV1389AQ
0.1 75
SIGNAL
Parallel clock data
STV1601A
SX
3
220 0.1 0.1 1
SY FV 33 RSE 28 TN1 35
4 220 -5V 0.1F 220 150 -5V 0.1F 2 150 75
10F SW2 10k VR1 -5V -5V 22k SIGNAL 270Mb/s SERIAL OUT t jitter = 1/2
1601A-18.EPS
10/17
1601A-17.EPS
10k
STV1601A
Figure 9 : tr, tf Definition serial data. To ease clock extraction at the receiving end, serial data is scrambled. To minimize polarity effect, serial data is then converted to NRZI and output in differential mode. A PLL lock detection circuit only enables the serial output when locked.
1601A-19.EPS
80%
20%
tr
tf
Figure 10 : td, tW Definition
tc t c /2 t c /2
1. Phase relation between input parallel clock and data The phase relation between the parallel clock and the data is shown in Figure 11. Both clock and data are differential inputs Parallel clock and data are such that the rising edge of PCX should be at the middle of the data. A clock having the same phase as PCX is internally generated in order to latch the data. 2. TTL input operation Parallel clock and data can be either TTL or ECL inputs. To use as TTL inputs VCC (Pin 29) shall be connected to +5V. A fixed bias of +1.4V shall be applied to PCY and DnY (n = 0 to 9). TTL signals and their parallel clock will be provided through 1kW resistors to each "X" input. These 1kW resistors are effective to minimize the influence of the TTL input signals to the jitter characteristics of the serial output signal. For 8-bit data, unused LSB(s) must be fixed Low. Fixed bias value can be higher, for example, 2.5V in case of CMOS inputs.
50%
1601A-20.EPS
td
tw
DESCRIPTION STV1601A internally generates a 10 times clock frequency locked to the parallel input clock thanks to a built-in PLLand converts input parallel data into Figure 11 : Phase Relation between Clock and Data
PCX (Input)
DATA (Input)
PCX (Output)
Figure 12 : TTL Input Operation
STV1601A
V CC 29 PCX 30 PCY 31 D9X 5 D9Y 7 D0X 26 D0Y 25
+ 5V
1k
1k
1k
+ 1.4V for TTL + 2.5V for CMOS
TTL Parallel Signal
11/17
1601A-22.EPS
Parallel Clock
Parallel Data
1601A-21.EPS
STV1601A
3. PLL block PARALLEL CLOCK INPUT CONTROL PLL, PLL lock detection and the various blocks of the serial output control are shown in Figure 13. When TN1 is connected to GND (set High), the parallel clock input is disabled. The VCO turns to free running conditions and its frequency can be adjusted through FV. This frequency decreases when the resistor value between FV and VEE is reduced. Oscillation frequency monotoring is performed through PCK which delivers a frequency divided by ten. When PLL is locked, PLL and PCX input signal phases are nearly matched. The RC network connected to TN1, temporarily, disables the parallel clock in order to avoid mislocking problems. VCO oscillation frequency range selection is available through RSE ; High : from 140 to 270MHz ; Low : from 100 to 145MHz. TRP (Pin 34) is the phase comparator output. To minimize jitter, a trap circuit, consisting in a serial tuned circuit at parallel clock frequency can be used. Figure 13 : PLL and Serial Output Control Block
PCY PCX TN1 TRP FV RSE PCK
PLL LOCK DETECTION The LST signal is generated by latching the incoming parallel clock by the internal one (which is 1/10 of the VCO frequency). LST is used as a PLL lock detection signal and also controls the serial output. If the parallel clock input is disabled (by means of TN1), LST turns Low and the serial output is disabled as described in the previous section (SX (Pin 3) = High, SY (Pin 4) = Low). If the serial output has to be disabled while no parallel clock input is provided, PCX must be set Low and PCY must be set High. 4. Sync word To convert serial data back to parallel, insertion of some timing reference data indicating the parallel data word boundary in the serial data is needed. This, called TRS (Timing Reference Signal) in the digital interface format, consists of the three consecutive words 3FFH, 000H, 000H. Conversion to 10-bit TRS from 8-bit (TRS) 8-bit parallel data 8-bit parallel data can be converted into 10-bit data by using the 8th bit as the MSB and by setting the 2 LSBs at logical states as shown in Figure 14.
PHASE COMPARATOR "0"
VCO
1/10 DIVIDER
LST
Q
D
SX
Q D NRZ To NRZI CONVERSION
SCRAMBLER
1601A-23.EPS
SY
Serial Clock
12/17
STV1601A
Figure 14 : 8-bit Parallel Input Data (ECL level) Figure 16 : (x9 + x 4 +1) Basic Scrambling Circuit
6
21
D1X 22
D1Y 23
D0X 24
D0Y 25
Figure 17 : (x9 + x4 +1) Basic Scrambling Circuit
10k
1601A-24.EPS
D1
D2
D3
D4
D6
D7
D8
D9
1601A-27.EPS
8-bit Parallel Data
V EE
D5
The conversion algorithm detects 2 successive 000H words and sets the two LSBs of the previous word, which is supposed to be FF, according to the standard. Figure 10 : Conversion from 8-bit TRS to 10-bit TRS
Input Order 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
To eliminate signal polarity of scrambled data, conversion from NRZ to NRZI is performed (Figures18 and 19). Therefore, the polarity for output distribution or receiving is not needed. This allows easy system design. The NRZ to NRZI polynominal is x + 1. VCO temperature compensation and oscillation frequency adjustment VCO oscillation frequency depends on the temperature as shown in Figures 22 and 23 "Representative characteristics examples". Within the normal range of operation, frequency increases with temperature. FV voltage remains almost constant regardless of temperature. Figure 20 shows an example of a temperature compensation circuit using a diode (transistor with C-B diode short-circuited) and a resistor connected between FV and VEE. Examplesof representativecharacteristics for various temperatures are shown in Figures 22 and 23 concerning oscillation frequency and PLL pull-in range (signal frequency 270, 177 and 143MHz). VCO free running frequency adjustment VCO free running frequency adjustment is performed at room temperature. If TN1 is set High, VCO free runs. Wait for 5 to 10 minutes after turning power supply ON (warm up time). While monitoring PCK output (Pin 36) adjust the signal frequency (within 1%) with the variable resistor connected between FV and VEE.
Input Data
Fixed Data
Input Parallel Data
Parallel Data after Conversion
Conversion in the case of more than three successive "000H" words. If more than 3 consecutive words of 000 in D1 standard, or 4 consecutive words of 000 in D2 standard occur at the parallel input (illegal according to the standard), thus no proper operation is possible. 5. Scrambling and NRZ to NRZI conversion Figures 16 and 17 show the scrambling circuit, the scrambling polynomial is as follows : x9 + x4 + 1.
1601A-25.EPS
LSB
13/17
1601A-26.EPS
STV1601A
D1
D2
D3
D4
D5
D6
D7
D8
D9
STV1601A
Figure 19 : Relation between NRZ and NRZI Signals
Time scale
NRZ signal
NRZI signal NRZ to NRZI conversion
NRZI signal
NRZI inverted signal
NRZ to NRZI conversion
Figure 20 : VCO Temperature Compensation and Free Running Adjustment
STV1601A
TN1 35 C1 10F 22k L1
10k
1601A-30.EPS
TRP 34
FV 33
PCK 36
Small signal transistor
Frequency monitor 1k
V EE
Jitter trap Since the internally generated serial clock is locked to the incoming parallel clock, there exists periodic jitter components which are generated from the phase comparison process of the PLL. A serial resonant circuit (trap) connected between TRP (Pin 34) and VEE tuned at the parallel clock frequency reduces effectively the fundamental component of the jitter well below the specification (0.25ns). Recommended values of C1 and L1 are given in the following table.
RECOMMENDED VALUES OF THE TRAP CIRCUIT COMPONENT C1 (pF) L1 (H) STANDARD D2 PAL NTSC 240 300 0.3 0.4
D1 150 0.2
An important remark in a practical implementation is that TRP node is an input of a very sensitive voltage-frequency converter (VCO) which can be easily disturbed by any pick-up noise. Hence, the trap circuit should be carefully located and be kept as short as possible from the Pin 34 in order to avoid noise problems.
14/17
1601A-29.EPS
220
220 7 4 SY
220 220
9 D9X -5V 220 -5V
0.1F 150
8 GND N.C. 37 Parallel Clock Test Ponit -5V 1k 22k
TN1 35 0.1F
6 SX GND LST For signal Processig 68
5
3
2
1
D8Y
D8X
D9Y
10 D7X
PCK 36 0.1F 0.1F
11 D7Y
1k
0.1F
Figure 21 : Application Circuit Example
12 D6X
10F/16V
Test Jumper
STV1389AQ
150 -5V
68
13 D6Y
C1 L1
TRP 34
Recommended values
For coaxial cable processing
FV 33 -5V
10k
14 D5X
STV1601A
(ENCODERMODULE)
GND 32 Q1 PCY 31 0.1
PCX 30
Parallel Data IN (ECL Balanced Pair)
D2 D1 Unit PAL NTSC C1 151 210 300 nF L1 0.2 0.3 0.4 H
15 D5Y
(Return) Parallel Clock In 0.1 4.7k 2.2k 51 51
16 D4X
-5V VCC 29 HIGH D1, D2 PAL 10k D2 NTSC VEE
27
17 D4Y
18 D3X
D1X D0X
24 25 26 22 23
RSE 28 (Rate select) D1Y D0Y V EE LOW
D3Y
D2X
D2Y
19
20
21
-5V ((115mA typical)
STV1601A
15/17
1601A-31.EPS
STV1601A
EXAMPLE OF REPRESENTATIVE CHARACTERISTICS Figure 22 : VCO Oscillation Frequency versus FV Pin Voltage
VCO oscillationfrequency (MHz)
300 RSE: "H" 25C 5C 45C 65C -15C 85C
Figure 23 : VCO Oscillation Frequency versus FV Pin Voltage
45C 25C RSE : "L"
VCO oscillationfrequency (MHz)
150 140 130 120 110
65C 5C 85C -15C
260
220 180
1601A-32.EPS
0.90
1.00
1.10
1.20
1.30
1.00
1.10 FV pin Voltage (V)
1.20
1.30
FV pin Voltage (V)
Figure 24 : Pull in Range and Free Run Frequency (270Mb/s)
30 29 28 27 26 25 24 23 -15 5 25 45 65 85 Ambient temperature (C) Low pull in
1601A-34.EPS
Figure 25 : Pull in Range and Free Run Frequency (177Mb/s)
21 Frequency (MHz) 20 19 18 17 16 15 14 -15 5 25 45 65 85 Ambient temperature (C) Low pull in
1601A-35.EPS
High pull in
High pull in
Frequency (MHz)
Free run
Free run
Figure 26 : Pull in Range and Free Run Frequency (143Mb/s)
18 Frequency (MHz) 17 16 15 14 13 12 11 -15 5 25 45 65 85 Ambient temperature (C) Low pull in
1601A-36.EPS
High pull in
Free run
16/17
1601A-33.EPS
140 0.80
100 0.90
STV1601A
PACKAGE MECHANICAL DATA 37 PINS - CERAMIC PGA
Dimensions in mm 3.8 25.4 0.5
0.2 Seating plane 1.15 0.15 1.2 4.2 0.1
0.46
0.05
Pin 19
2.54 x 9 = 22.86
0.25
Pin 28
0.25
2.54 x 9 = 22.86
Pin 36 Pin 37 2.54
25.4
Bottom View
0.5
Pin 10
2.032 max.
2.54
Pin 1
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
17/17
PM-PGA37.EPS

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